1. Field of the Invention
The present invention relates generally to the field of microprocessors and more specifically to single-endian microprocessors that are compatible with bi-endian systems.
2. Art Background
Byte ordering determines how data is read from or written to memory and buses and ultimately how data is stored in the memory. The two byte ordering types are referred to as little endian and big endian. Consider a word having bytes A, B, C, and D where A is the most significant byte, B is the next most significant byte, C is the third most significant byte, and D is the least significant byte. Little endian systems store words in which the least significant byte is at the lowest address in memory. If a little endian ordered word is stored at 1000H, for example, D is stored at 1000H, C is stored at 1001H, B is stored at 1002H, and A is stored at 1003H, i.e. ABCD. A big endian ordered word stores the least significant byte at the highest byte address in memory. Therefore, if a big endian word is stored at 1000H, A is stored at 1000H, B is stored at 1001H, C is stored at 1002H, and D is stored at 1003H, i.e. DCBA.
Typically, a processor will operate in either a little endian or big endian mode and the bus attached to the processor operates in the same mode. Although some processors can operate either in the big endian mode or little endian mode, most processors typically operate in one mode and perform, as necessary, a translation of data received from a memory or other external devices prior to use by the processor. For example, processors manufactured by Intel Corporation use little endian format internally. Therefore, the processor performs operations in little endian format and likewise the internal bus which connects the processor is also little endian. Translations are performed prior to use by the processor, for example at the bus controller, so that the information is in the proper format prior to receipt by the processor.
The typical translation converts big endian ordered data to little endian ordered data, or vice versa, by switching the order of the bytes. For example, in processors manufactured by Intel Corporation, a big endian ordered word DCBA received by the microprocessor is converted to little endian ABCD by the bus controller before being placed on the internal bus. Likewise, when the processor stores little endian data ABCD to a big endian external memory, the bus controller converts the data to DCBA before storing. Thus, the translation is performed during both load and store accesses to big endian ordered memory locations.
However, this byte ordering translation does not correctly handle byte and short accesses to big endian ordered memory where a processor has a little endian data cache or where a little endian processor promotes cacheable byte or short (two bytes) accesses to word accesses. For example, big endian ordered data DCBA is stored at memory location 1000H. A copy of the big endian data is stored at 1000H in the data cache unit in little endian format as ABCD. Suppose that the processor requests byte data D at 1003H. In a first case, the access "hits" the data cache. But data A at 1003H in the data cache is not a copy of data D at 1003H in external memory. Therefore, the data cache returns incorrect data to the processor. Effectively the same result occurs in a second case when the byte access does not hit the data cache. In that case the byte access to 1003H is promoted to a word access to 1000H by the bus controller. The bus controller returns, after byte ordering translation, ABCD to the internal bus. Again, data A returned to the internal bus at the position corresponding to 1003H is not the same as data D at 1003H in external memory.
Therefore, a method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor is needed.